1. Field of the Invention
This invention relates generally to the packaging of semiconductor chips on leadframes, and more particularly to plastic flat packages (PFP) for integrated circuit chips which packages have enhanced thermal conduction properties and a technique for improving the utilization of the contact pads on the chip to allow more versatility in the design of the function of the various connections on the chip.
The progress in the design and manufacture of integrated circuit chips has resulted in an increased number of circuits and functions which can be provided on any size chip, and hence a need for an increased number of bonding pads on the periphery of a chip of any given dimension for signal input/output (I/O), voltage, and grounding. As the number of these pads increases and the size of the pads decreases, it is increasingly difficult to provide reliable connections to the individual pads for the necessary signals or voltage levels or ground levels which must be supplied to the various circuits on the chip.
One conventional technique for packaging chips is by utilizing leadframes which have fingers radiating therefrom, which fingers surround a central portion of the leadframe on which the chip is mounted. The leadframe fingers can be directly attached to the bonding pads on the chip, but this becomes more and more difficult to accomplish as the size of the pads, as well as the spacing between the pads on the chips decreases with the attendant increase in the number of bonding pads available.
Hence, it has become conventional in many instances to terminate the lead fingers a distance from the chip to thereby provide a larger geometrical area for the termination location of the fingers, and connect the various fingers to the pads on the chip by means of various wire bonding techniques. In such a technique, conventionally a certain number of pads on the chip, which are the voltage level pads must be connected to fingers directly across from them to provide the necessary voltage, thereby requiring that a certain number of fingers be dedicated to the provision of the voltage level. Similarly, a certain number of the pads must be connected to ground level voltage which also requires a certain number of fingers on the leadframe to be connected to ground level Conventionally, these fingers which are connected to the voltage and to the ground level are interposed or interdigitated between the other fingers on the leadframe which other fingers provide the necessary input/output signals to the pads on the chip. Thus, with these conventional prior art techniques, a significant number of the leadframe fingers must be dedicated to either providing various voltage power levels or ground levels for the chips.
In addition to reducing the number of fingers dedicated to I/O signals, the use of interdigitated fingers for both voltage and signals may introduce unwanted induction in the signal lines with the resulting potential for creating errors in the signals. Moreover, even by spacing the ends of the fingers a distance from the edge of the chip, it is still difficult to provide the required number of fingers for contact because the distance that the wire interconnections can span between the chip and the fingers are limited, and thus the ends of the fingers cannot terminate at a distance too far from the edge of the chip for effective wire interconnection. This, coupled with the fact that the fingers must have certain minimum widths and spacing further adds to the problem of providing a sufficient number of interconnections for all of the pads on various chips.
Another problem encountered by package designers and chips designers is that even if a sufficient number of fingers can be provided at the proper distance from the chip, it is generally necessary that each finger be wired to a chip bond connection directly across from the finger, i.e. it is difficult to provide connections of pads to fingers which are not directly opposite therefrom because of the necessary crossing of wires can cause significant problems.
Frequently, a chip designer must design a predetermined PFP lead configuration where voltage and/or ground lead locations have been fixed. Most configurations do not have voltage ground programmability (i.e. allow for selection of lines for ground and/or voltage connections) and require chip redesign. U.S. Pat. No. 4,835,120 to Mallik, et al. is an exception to this which discloses the use of multilevel tape which in turn is bonded to a metal plate which mounts the chip. This requires three metal planes separated by insulators.
Japanese Kokai 56-76864, assigned to Stanley Denke K K, discloses a standard leadframe secured to a ceramic with a wiring pattern on the ceramic. This holds the fingers together with the ceramic to keep them from breaking.
U.S. Pat. No. 4,916,506, assigned to Sprague Electric Company, discloses a conventional DIP wire bond of a chip to a leadframe wherein each pad on the chip is connected to a finger on the leadframe.
Japanese Kokai 55-164559, assigned to Hitachi Seisakusho K. K. discloses a standard wire bonding technique wire bonding chip pads to fingers on a leadframe wherein the chip is rotated 45.degree. to provide improved wire geometry.
Japanese Kokai 62-123750 to Hitachi discloses a standard DIP package and relates to cutting of the salvage.
Japanese Kokai 1-102945 to NEC Kyushu Ltd. discloses a technique for plating the element mounting part.
Japanese Kokai 59-191360 discloses a double tiered DIP package.
U.S. Pat. No. 3,967,366 to Birglechner, et al. discloses a leadframe tied to a thermal fin which constitutes a part of the leadframe and utilizes a second leadframe stacked on the first leadframe over the top of the chip.
U.S. Pat. No. 4,800,419, to LSI Logic Corporation, discloses a leadframe mounted on the die pedestal.
The article entitled "Thermal Characteristics Of Single and Multi-layer High Performance PQFP Packages" by Aghazadeh, et al. Sixth IEEE; THERM Symposium thermal characteristics of single and multilayer high performance packages.
The article "High Performance PQFP" by Mallik, et al. in IEEE discloses various wire lead configurations, which are aimed at electrical and thermal improvements by the introduction of additional metal planes disclosed U.S. Pat. No. 4,835,120, but does not provide a solution for decreasing chip size and finer wire bond chip pitch.
In net, prior art shows a segment of industry seeking solutions to smaller chips and tighter wire bond pitches; and a second segment seeking solutions to improve thermal and electrical characteristics. The results do not offer an economic technical solution to the composite set of problems. The invention which follows provides a solution to both problems and further extends the technical advantage of the leadframe technology relative to physical dimensions and reliability.